Problem Statement

"Simulate" a four-bit adder. This design can be realized using four 1-bit full adders. Each of these 1-bit full adders can be built with two half adders and an   or   gate. ; Finally a half adder can be made using an   xor   gate and an   and   gate. The   xor   gate can be made using two   nots,   two   ands   and one   or. Not,   or   and   and,   the only allowed "gates" for the task, can be "imitated" by using the bitwise operators of your language. If there is not a bit type in your language, to be sure that the   not   does not "invert" all the other bits of the basic type   (e.g. a byte)   we are not interested in,   you can use an extra   nand   (and   then   not)   with the constant   1   on one input. Instead of optimizing and reducing the number of gates used for the final 4-bit adder,   build it in the most straightforward way,   connecting the other "constructive blocks",   in turn made of "simpler" and "smaller" ones.

Solutions should try to be as descriptive as possible, making it as easy as possible to identify "connections" between higher-order "blocks". It is not mandatory to replicate the syntax of higher-order blocks in the atomic "gate" blocks, i.e. basic "gate" operations can be performed as usual bitwise operations, or they can be "wrapped" in a block in order to expose the same syntax of higher-order blocks, at implementers' choice. To test the implementation, show the sum of two four-bit numbers (in binary).

Let's start with the solution:

⍝ Our primitive "gates" are built-in, but let's give them names
not ← { ~ ⍵ }   ⍝ in Dyalog these assignments can be simplified to "not ← ~", "and ← ∧", etc.
and ← { ⍺ ∧ ⍵ }
or ← { ⍺ ∨ ⍵ }

⍝ Build the complex gates
nand ← { not ⍺ and ⍵ } ⍝ similarly this can be built with composition as "nand ← not and"
xor ← { (⍺ and not ⍵) or (⍵ and not ⍺) }

⍝ And the multigate components. Our bit vectors are MSB first, so for consistency
⍝ the carry bit is returned as the left result as well.
half_adder ← { (⍺ and ⍵), ⍺ xor ⍵ } ⍝ returns carry, sum

⍝ GNU APL dfns can't have multiple statements, so the other adders are defined as tradfns
∇result ← c_in full_adder args ; c_in; a; b; s0; c0; s1; c1
 (a b) ← args
 (c0 s0) ← c_in half_adder a
 (c1 s1) ← s0 half_adder b
 result ← (c0 or c1), s1
∇

⍝ Finally, our four-bit adder
∇result ← a adder4 b ; a3; a2; a1; a0; b3; b2; b1; b0; c0; s0; c1; s1; c2; s2; s3; v
 (a3 a2 a1 a0) ← a
 (b3 b2 b1 b0) ← b
 (c0 s0) ← 0 full_adder a0 b0
 (c1 s1) ← c0 full_adder a1 b1
 (c2 s2) ← c1 full_adder a2 b2
 (v s3) ← c2 full_adder a3 b3
 result ← v s3 s2 s1 s0
∇

⍝ Add one pair of numbers and print as equation
demo ← { 0⍴⎕←⍺,'+',⍵,'=',{ 1↓⍵,' with carry ',1↑⍵ } ⍺ adder4 ⍵ }

⍝ A way to generate some random numbers for our demo
randbits ← { 1-⍨?⍵⍴2 }

⍝ And go
{ (randbits 4) demo randbits 4 ⊣ ⍵ } ¨ ⍳20